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mitsubishi microcomputers 7630 group 1 mitsubishi electric single-chip 8-bit cmos microcomputer description the 7630 g roup is a sin g le chip 8-bit microcomputer desi g ned with cmos silicon g ate technolo g y. bein g equipped with a can (controller area network) module cir- cuit, the microcomputer is suited to drive automotive equipments. the can module complies with can specification version 2.0, part b and allows priority-based messa g e mana g ement. in addition to the microcomputers simple instruction set, the rom, ram and i/o addresses are placed in the same memory map to enable easy pro g rammin g . the built-in rom is available as mask rom or one time prom. for development purposes, emulator- and eprom-type microcom- puters are available as well. features z basic machine-lan g ua g e instructions . . . . . . . . . . . . . . . . . . 71 z minimum instruction execution time (at 10 mhz oscillation frequency) . . . . . . . . . . . . . . . . . . 0.2 m s z memory size rom . . . . . . . . . . . . . . . . .16252 bytes (m37630m4t-xxxfp) ram . . . . . . . . . . . . . . . . . . .512 bytes (m37630m4t-xxxfp) z i/o ports pro g rammable i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 z interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors z timers 16-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels 8-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels z serial i/os clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel z can module (can specification version 2.0, part b) . . . . . . . . . . . 1 channel z a-d converter . . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels z watchdo g timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 z clock generatin g circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 built-in with internal feedback resistor z power source volta g e (at 10 mhz oscillation frequency). . . . . . . . . . . . . . . 4.0 to 5.5 v z power dissipation in hi g h-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mw (at 8 mhz oscillation frequency, at 5 v power source volta g e) z operatin g temperature ran g e. . . . . . . . . . . . . . . . . C40 to 85 c z packa g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44qfp (44p6n-a) application automotive controls fig. 1 pin configuration of m37630m4tCxxxfp 34 22 35 21 36 20 37 19 38 18 39 17 40 16 41 15 42 14 43 13 44 12 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 m37630m4t-xxxfp m37630e4t-xxxfp p1 7 p2 0 /s in p2 1 /s out p2 2 /s clk p2 3 /s rdy v ss p2 4 /ur x d p2 5 /ut x d p2 6 /u rts p2 7 /u cts p3 0 p0 2 /an 2 p0 1 /an 1 p0 0 /an 0 v ref av ss v cc x out x in v ss reset p4 7 /kw 7 p1 6 /pwm p1 5 /cntr 1 p1 4 /cntr 0 p1 3 /tx 0 p1 2 /int 1 p1 1 /int 0 p0 7 /an 7 p0 6 /an 6 p0 5 /an 5 p0 4 /an 4 p0 3 /an 3 p3 1 /ctx p3 2 /crx p3 3 p3 4 p4 0 /kw 0 p4 1 /kw 1 p4 2 /kw 2 p4 3 /kw 3 p4 4 /kw 4 p4 5 /kw 5 p4 6 /kw 6 package type: 44p6n-a pin configuration (top view) 44-pin plastic molded qfp
mitsubishi electric 2 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 2 functional block diagram 20 21 22 23 24 25 26 27 p0 (8) 19 8 28 29 30 31 32 33 34 p1 (7) 35 36 37 38 40 41 42 p2 (8) 43 44 1 2 3 4 p3 (5) 15 16 13 17 14 39 18 ram rom v ref input i/o port p0 i/o port p1 i/o port p2 i/o port p3 3 4 uart 4 serial i/o can 2 5 6 7 8 9 10 11 p4 (8) 12 i/o port p4 key on wake up clock generating circuit a (8) x (8) y (8) s (8) pc l (8) ps (8) pc h (8) cpu timer x (16) timer y (16) timer 1 (8) timer 2 (8) timer 3 (8) pwm int 0 , int 1 a-d converter 2 clock output x out clock input x in reset input reset v cc v ss av ss m37630mxt-xxxfp functional block diagram (package: 44p6n-a) wdt 2
mitsubishi microcomputers 7630 group 3 mitsubishi electric single-chip 8-bit cmos microcomputer pin description table 1: pin description pin name input/output description v cc , v ss power source volta g e power supply pins; apply 4.0 to 5.5 v to v cc and 0 v to v ss av ss analo g power source volta g e ground pin for a-d converter. connect to v ss reset reset input input reset pin. this pin must be kept at l level for more than 2 m s, to enter the reset state. if the crystal or ceramic resonator requires more time to stabilize, extend the l level period. x in clock input input input and output pins of the internal clock g eneratin g circuit. connect a ceramic or quartzCcrystal resonator between the x in and x out pins. when an external clock source is used, connect it to x in and leave x out open. x out clock output output v ref reference volt- a g e input input reference volta g e input pin for a-d converter p0 0 /an 0 p0 7 /an 7 i/o port p0 i/o cmos i/o ports or analo g input ports p1 1 /int 0 input cmos input port or external interrupt input port. the active ed g e (risin g or fallin g ) of external interrupts can be selected. this pin will be used as v pp pin durin g prom pro g rammin g of one time prom versions. p1 2 /int 1 cmos i/o port or external interrupt input port. the active ed g e (risin g or fallin g ) of external interrupts can be selected. p1 3 /tx 0 cmos i/o port or input pin used in the bi-phase counter mode p1 4 /cntr 0 i/o port p1 i/o cmos i/o port or timer x input pin used for the event counter, pulse width measure- ment and bi-phase counter mode p1 5 /cntr 1 cmos i/o port or timer y input pin used for the event counter, pulse width and pulse period measurement mode p1 6 /pwm cmos i/o port or pwm output pin used in the pwm mode of timers 2 and 3 p1 7 cmos i/o port p2 0 /s in p2 1 /s out p2 2 /s clk p2 3 /s rdy cmos i/o ports or clock synchronous serial i/o pins p2 4 /ur x d p2 5 /ut x d p2 6 /u rts p2 7 /u cts cmos i/o ports or asynchronous serial i/o pins p3 0 cmos i/o port p3 1 /ctx cmos i/o port or can transmit data pin p3 2 /crx cmos i/o port or can receive data pin p3 3 p3 4 cmos i/o port p4 0 /kw 0 p4 7 /kw 7 i/o port p4 i/o cmos i/o ports. these ports can be used for key-on wake-up when confi g ured as inputs. i/o port p2 i/o port p3 i/o i/o
mitsubishi electric 4 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer part numbering fig. 3 part numbering product m37630 m 4 tC xxx fp packa g e type fp: 44p6n-a packa g e fs: 80d0 packa g e rom number omitted in one time prom version (blank) and eprom version t: automotive use rom/prom size 4: 16384 bytes the first 128 bytes and the last 4 bytes of rom are reserved areas. they cannot be used. memory type m: mask rom version e: eprom or one time prom version
mitsubishi microcomputers 7630 group 5 mitsubishi electric single-chip 8-bit cmos microcomputer group expansion mitsubishi plans to expand the 7630 g roup as follows: memory type support mask rom, one time prom and eprom versions. memory size rom/prom size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kbytes ram size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes package 44p6n-a . . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded qfp 80d0 . . . . . . . . . . .0.8mm-pitch ceramic lcc (eprom version) fig. 4 memory expansion plan currently supported products are listed below: rom external 60k 48k 32k 28k 24k 20k 16k 12k 8k 384 512 640 768 896 1024 ram size (bytes) m37630m4t m37630e4t under development mass product table 2: list of supported products product (p)rom size (bytes) rom size for user ( ) ram size (bytes) packa g e remarks m37630m4t-xxxfp mask rom version m37630e4t-xxxfp 16384 512 44p6n-a one time prom version m37630e4fp (16252) one time prom version (blank) m37630e4fs 80d0 eprom version as of march 1998
mitsubishi electric 6 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer functional description central processing unit (cpu) the core of 7630 g roup microcomputers is the 7600 series cpu. this core is based on the standard instruction set of 740 series; however the performance is improved by allowin g to execute the same instructions as that of the 740 series in less cycles. refer to the 7600 series software manual for details of the instruction set. cpu mode register cpum the cpu mode re g ister contains the stack pa g e selection bit and internal system clock selection bit. the cpu mode re g ister is allo- cated to address 0000 16 . fig. 5 structure of cpu mode register cpu mode re g ister (address 0000 16 ) cpum processor mode bits (set these bits to 00) b1 b0 0 0: sin g leCchip mode 0 1: not used 1 0: not used 1 1: not used stack pa g e selection bit 0 : 0 pa g e 1 : 1 pa g e not used (0 when read, do not write 1) internal system clock selection bit 0 : f= f(x in ) divided by 2 (hi g hCspeed mode) 1 : f= f(x in ) divided by 8 (middleCspeed mode) not used (0 when read, do not write 1) 70
mitsubishi microcomputers 7630 group 7 mitsubishi electric single-chip 8-bit cmos microcomputer memory special function register (sfr) area the special function re g ister (sfr) area contains the re g isters relatin g to functions such as i/o ports and timers. ram ram is used for data stora g e and for stack area of subroutine calls and interrupts. rom rom is used for storin g users pro g ram code as well as the inter- rupt vector area. interrupt vector area the interrupt vector area is for storin g jump destination addresses used at reset or when an interrupt is g enerated. zero page this area can be accessed most efficiently by means of the zero pa g e addressin g mode. special page this area can be accessed most efficiently by means of the special pa g e addressin g mode. fig. 6 memory map diagram 0040 16 0000 16 00ff 16 0060 16 xxxx 16 yyyy 16 zzzz 16 ff00 16 ffca 16 fffb 16 fffc 16 ffff 16 sfr area not used reserved rom area interrupt vector area reserved rom area zero pa g e special pa g e can sfrs ram area ram size (byte) address xxxx 16 192 011f 16 256 015f 16 384 01df 16 512 025f 16 640 02df 16 768 035f 16 896 03df 16 1024 045f 16 1536 06df 16 2048 085f 16 rom area rom size (byte) address yyyy 16 address zzzz 16 4096 f000 16 f080 16 8192 e000 16 e080 16 12288 d000 16 d080 16 16384 c000 16 c080 16 20480 b000 16 b080 16 24576 a000 16 a080 16 28672 9000 16 9080 16 32768 8000 16 8080 16 36864 7000 16 7080 16 40960 6000 16 6080 16 45056 5000 16 5080 16 49152 4000 16 4080 16 53248 3000 16 3080 16 57344 2000 16 2080 16 61440 1000 16 1080 16 user ram rom 0860 16
mitsubishi electric 8 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer special function registers (sfr) fig. 7 memory map of special register (sfr) 0030 16 can transmit control re g ister ctrm 0031 16 can bus timin g control re g ister 1 cbtcon1 0032 16 can bus timin g control re g ister 2 cbtcon2 0033 16 can acceptance code re g ister 0 cac0 0034 16 can acceptance code re g ister 1 cac1 0035 16 can acceptance code re g ister 2 cac2 0036 16 can acceptance code re g ister 3 cac3 0037 16 can acceptance code re g ister 4 cac4 0038 16 can acceptance mask re g ister 0 cam0 0039 16 can acceptance mask re g ister 1 cam1 003a 16 can acceptance mask re g ister 2 cam2 003b 16 can acceptance mask re g ister 3 cam3 003c 16 can acceptance mask re g ister 4 cam4 003d 16 can receive control re g ister crec 003e 16 can transmit abort re g ister cabort 003f 16 reserved 0040 16 can transmit buffer re g ister 0 ctb0 0041 16 can transmit buffer re g ister 1 ctb1 0042 16 can transmit buffer re g ister 2 ctb2 0043 16 can transmit buffer re g ister 3 ctb3 0044 16 can transmit buffer re g ister 4 ctb4 0045 16 can transmit buffer re g ister 5 ctb5 0046 16 can transmit buffer re g ister 6 ctb6 0047 16 can transmit buffer re g ister 7 ctb7 0048 16 can transmit buffer re g ister 8 ctb8 0049 16 can transmit buffer re g ister 9 ctb9 004a 16 can transmit buffer re g ister a ctba 004b 16 can transmit buffer re g ister b ctbb 004c 16 can transmit buffer re g ister c ctbc 004d 16 can transmit buffer re g ister d ctbd 004e 16 reserved 004f 16 reserved 0050 16 can receive buffer re g ister 0 crb0 0051 16 can receive buffer re g ister 1 crb1 0052 16 can receive buffer re g ister 2 crb2 0053 16 can receive buffer re g ister 3 crb3 0054 16 can receive buffer re g ister 4 crb4 0055 16 can receive buffer re g ister 5 crb5 0056 16 can receive buffer re g ister 6 crb6 0057 16 can receive buffer re g ister 7 crb7 0058 16 can receive buffer re g ister 8 crb8 0059 16 can receive buffer re g ister 9 crb9 005a 16 can receive buffer re g ister a crba 005b 16 can receive buffer re g ister b crbb 005c 16 can receive buffer re g ister c crbc 005d 16 can receive buffer re g ister d crbd 005e 16 reserved 005f 16 reserved 0000 16 cpu mode re g ister cpum 0001 16 not used 0002 16 interrupt request re g ister a ireqa 0003 16 interrupt request re g ister b ireqb 0004 16 interrupt request re g ister c ireqc 0005 16 interrupt control re g ister a icona 0006 16 interrupt control re g ister b iconb 0007 16 interrupt control re g ister c iconc 0008 16 port p0 re g ister p0 0009 16 port p0 direction re g ister p0d 000a 16 port p1 re g ister p1 000b 16 port p1 direction re g ister p1d 000c 16 port p2 re g ister p2 000d 16 port p2 direction re g ister p2d 000e 16 port p3 re g ister p3 000f 16 port p3 direction re g ister p3d 0010 16 port p4 re g ister p4 0011 16 port p4 direction re g ister p4d 0012 16 serial i/o shift re g ister sio 0013 16 serial i/o control re g ister siocon 0014 16 a-d conversion re g ister ad 0015 16 a-d control re g ister adcon 0016 16 timer 1 t1 0017 16 timer 2 t2 0018 16 timer 3 t3 0019 16 timer 123 mode re g ister t123m 001a 16 timer xl txl 001b 16 timer xh txh 001c 16 timer yl tyl 001d 16 timer yh tyh 001e 16 timer x mode re g ister txm 001f 16 timer y mode re g ister tym 0020 16 uart mode re g ister umod 0021 16 uart baud rate g enerator ubrg 0022 16 uart control re g ister ucon 0023 16 uart status re g ister usts 0024 16 uart transmit buffer re g ister 1 utbr1 0025 16 uart transmit buffer re g ister 2 utbr2 0026 16 uart receive buffer re g ister 1 urbr1 0027 16 uart receive buffer re g ister 2 urbr2 0028 16 port p0 pull-up control re g ister pup0 0029 16 port p1 pull-up control re g ister pup1 002a 16 port p2 pull-up control re g ister pup2 002b 16 port p3 pull-up control re g ister pup3 002c 16 port p4 pull-up/down control re g ister pup4 002d 16 interrupt polarity selection re g ister ipol 002e 16 watchdo g timer re g ister wdt 002f 16 polarity control re g ister pcon
mitsubishi microcomputers 7630 group 9 mitsubishi electric single-chip 8-bit cmos microcomputer i/o ports the 7630 g roup has 35 pro g rammable i/o pins and one input pin arran g ed in five i/o ports (ports p0 to p4). the i/o ports are con- trolled by the correspondin g port re g isters and port direction re g is- ters; each i/o pin can be controlled separately. when data is read from a port confi g ured as an output port, the port latchs contents are read instead of the port level. a port confi g ured as an input port becomes floatin g and its level can be read. data written to this port will affect the port latch only; the port remains floatin g . refer to structure of port- and port direction re g isters, structure of port i/os (1) and structure of port i/os (2). fig. 8 structure of port- and port direction registers port pi j direction control bit (j = 0 to 7) 0 : port confi g ured as input 1 : port confi g ured as output note : the direction control bits corresponding to p1 0 , p1 1 , p3 5 , p3 6 and p3 7 are not used (0 when read, do not write 1). port direction re- gisters are undefined when read (write only). 70 port pi direction re g ister (i = 0 to 4) (address 0009 16 + 2 i) pid port pi j control bit (j = 0 to 7) 0 : l level 1 : h level note : the control bits corresponding to p1 0 , p3 5 , p3 6 and p3 7 are not used (0 when read, do not write 1). 70 port pi re g ister (i = 0 to 4) (address 0008 16 + 2 i) pi
mitsubishi electric 10 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 9 structure of port i/os (1) (1) ports p0 0 /an 0 to p0 7 /an 7 (2) port p1 1 /int 0 data bus interrupt input (3) port p1 2 /int 1 data bus pull-up control bit port latch direction register interrupt input (4) port p1 3 /tx 0 data bus pull-up control bit port latch direction register timer bi-phase mode input (5) ports p1 4 /cntr 0 , p1 5 /cntr 1 data bus pull-up control bit port latch direction register timer bi-phase mode input (6) port p1 6 /pwm data bus pull-up control bit port latch direction register pwm output pwm output enable data bus pull-up control bit port latch direction register adc input analog input selection analog input selection
mitsubishi microcomputers 7630 group 11 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 10 structure of port i/os (2) (13) ports p2 5 /ut x d, p2 6 /u rts (14) port p3 1 /ctx (15) port p3 2 /crx data bus can dominant level control bit port latch (16) ports p4 0 /kw 0 to p4 7 /kw 7 data bus pull-up control bit port latch direction register transmission or reception** in progress transmit or receive** enable bit u txd or u rts output data bus pull-up control bit port latch direction register can port selection bit ctx output direction register pull-up /down control bit can interrupt crx input data bus key-on wake-up control bit port latch direction register pull-up /down control bit key-on wake-up interrupt (9) port p2 1 /s out data bus pull-up control bit port latch direction register sio output sio port selection bit transmit complete signal (10) port p2 2 /s clk data bus pull-up control bit port latch direction register sio clock output clock selection bit port selection bit external clock input (11) port p2 3 /s rdy data bus pull-up control bit port latch direction register srdy output srdy output selection bit (12) ports p2 4 /ur x d, p2 7 /u cts data bus pull-up control bit port latch direction register transmission or reception* in progress transmit or receive* enable bit u rxd or u cts input (7) ports p1 7 , p3 0 , p3 3 , p3 4 data bus pull-up control bit port latch direction register (8) port p2 0 /s in data bus pull-up control bit port latch direction register sio1 input (*) for u cts (**) for u rts sio port select
mitsubishi electric 12 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer port pull-up/pull-down function each pin of ports p0 to p4 except p1 1 is equipped with a pro g ram- mable pull-up transistor. p3 2 /crx and p4 0 /kw 0 to p4 7 /kw 7 are equipped with pro g rammable pull-down transistors as well. the pull-up function of p0 to p3 can be controlled by the correspondin g port pull-up control re g isters (see structure of port pull-up/down control re g isters). the pull-up/down function of ports p3 2 and p4 can be controlled by the correspondin g port pull-up/pull-down re g is- ters to g ether with the polarity control re g ister (see structure of polarity control re g ister). fig. 11 structure of port pull-up/down control registers fig. 12 structure of polarity control register p3 j pull-up transistor control bit (j = 0, 1) p3 2 pull-up/down transistor control bit p3 j pull-up transistor control bit (j = 3, 4) not used (0 when read, do not write 1) pi j pull-up transistor control bit (j = 0 to 7) 0 : pull-up transistor disabled 1 : pull-up transistor enabled 70 port pi pull-up control re g ister (address 0028 16 + i) (i = 0, 2) pup0, pup2 70 port p1 pull-up control re g ister (address 0029 16 ) pup1 70 port p3 pull-up control re g ister (address 002b 16 ) pup3 p4 j pull-up/down transistor control bit (j = 0 to 7) 70 not used (0 when read, do not write 1) p1 j pull-up transistor control bit (j = 2 to 7) 0 : pull-up/down transistor disabled 1 : pull-up/down transistor enabled port p4 pull-up/down control re g ister (address 002c 16 ) pup4 key-on wake-up polarity control bit 0 : low level active 1 : hi g h level active can module dominant level control bit 0 : low level dominant 1 : hi g h level dominant not used (undefined when read) 70 polarity control re g ister (address 002f 16 ) pcon
mitsubishi microcomputers 7630 group 13 mitsubishi electric single-chip 8-bit cmos microcomputer port overvoltage application when confi g ured as input ports, p1 to p4 may be subjected to over- volta g e (v i >v cc ) if the input current to the applicable port is limited to the specified values (see table 8:). use a serial resistor of appropriate size to limit the input current. to estimate the resistor value, assume the port volta g e to be v cc at overvolta g e condition. notes: ? subjectin g ports to overvolta g e may effect the supply volta g e. assure to keep v cc and v ss within the tar g et limits. ? avoid to subject ports to overvolta g e causin g v cc to rise above 5.5 v. ? the overvolta g e condition causin g input current flowin g throu g h the internal port protection circuits has a ne g ative effect on the ports noise immunity. therefore, careful and intense testin g of the tar g et systems noise immunity is required. refer to the countermeasures a g ainst noise of the correspondin g users manual. ? port p0 must not be subjected to overvolta g e conditions.
mitsubishi electric 14 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer interrupts there are 24 interrupts: 6 external, 17 internal, and 1 software. interrupt control each interrupt except the brk instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable fla g . an interrupt occurs when the correspond- in g interrupt request and enable bits are 1 and the interrupt dis- able fla g is 0. interrupt enable bits can be cleared or set by software. interrupt request bits can be cleared by software but can- not be set by software. the brk instruction interrupt and reset can- not be disabled with any fla g or bit. the i fla g disables all interrupts except the brk instruction interrupt and reset. if several interrupt requests occur at the same time, the interrupt with the hi g hest prior- ity is accepted first. interrupt operation upon acceptance of an interrupt, the followin g operations are auto- matically performed. 1. the processin g bein g executed is stopped. 2. the contents of the pro g ram counter and processor status re g ister are automatically pushed onto the stack. 3. concurrently with the push operation, the interrupt jump destination address is read from the vector table into the pro g ram counter. 4. the interrupt disable fla g is set and the correspondin g interrupt request bit is cleared. notes on use when the active ed g e of an external interrupt (int 0 , int 1 , cntr 0 , cntr 1 , cwku or koi) is chan g ed, the correspondin g interrupt request bit may also be set. therefore, take the followin g sequence. (1) disable the external interrupt which is selected. (2) chan g e the active ed g e in interrupt ed g e selection re g ister. (in the case of cntr 0 : timer x mode re g ister; in the case of cntr 1 : timer y mode re g ister) (3) clear the interrupt request bit to 0. (4) enable the external interrupt which is selected.
mitsubishi microcomputers 7630 group 15 mitsubishi electric single-chip 8-bit cmos microcomputer . table 3: interrupt vector addresses and priority interrupt source priority vector address (note 1) interrupt request generatin g conditions remarks hi g h low reset (note 2) 1 fffb 16 fffa 16 at reset non-maskable watchdo g timer 2 fff9 16 fff8 16 at watchdo g timer underflow non-maskable int 0 3 fff7 16 fff6 16 at detection of either risin g or fallin g ed g e of int 0 interrupt external interrupt (active ed g e selectable) int 1 4 fff5 16 fff4 16 at detection of either risin g or fallin g ed g e of int 1 interrupt external interrupt (active ed g e selectable) can successful transmit 5 fff3 16 fff2 16 at can module successful transmission of messa g e valid when can module is activated and request transmit can successful receive 6 fff1 16 fff0 16 at can module successful reception of messa g e valid when can module is activated can overrun 7 ffef 16 ffee 16 if can module receives messa g e when receive buffers are full. valid when can module is activated can error passive 8 ffed 16 ffec 16 when can module enters into error passive state valid when can module is active can error bus off 9 ffeb 16 ffea 16 when can module enters into bus off state valid when can module is active can wake up 10 ffe9 16 ffe8 16 when can module wakes up via can bus timer x 11 ffe7 16 ffe6 16 at timer x underflow or overflow timer y 12 ffe5 16 ffe4 16 at timer y underflow timer 1 13 ffe3 16 ffe2 16 at timer 1 underflow timer 2 14 ffe1 16 ffe0 16 at timer 2 underflow timer 3 15 ffdf 16 ffde 16 at timer 3 underflow cntr 0 16 ffdd 16 ffdc 16 at detection of either risin g or fallin g ed g e in cntr 0 input external interrupt (active ed g e selectable) cntr 1 17 ffdb 16 ffda 16 at detection of either risin g or fallin g ed g e in cntr 1 input external interrupt (active ed g e selectable) uart receive 18 ffd9 16 ffd8 16 at completion of uart receive valid when uart is selected uart transmit 19 ffd7 16 ffd6 16 at completion of uart transmit valid when uart is selected uart transmit buffer empty 20 ffd5 16 ffd4 16 at uart transmit buffer empty valid when uart is selected uart receive error 21 ffd3 16 ffd2 16 when uart reception error occurs. valid when uart is selected serial i/o 22 ffd1 16 ffd0 16 at completion of serial i/o data transmit and receive valid when serial i/o is selected a-d conversion 23 ffcf 16 ffce 16 at completion of a-d conversion key-on wake-up 24 ffcd 16 ffcc 16 at detection of either risin g or fallin g ed g e of p4 input external interrupt (active ed g e selectable) brk instruction 25 ffcb 16 ffca 16 at brk instruction execution non-maskable notes 1: vector addresses contain interrupt jump destination address 2: reset function in the same way as an interrupt with the hi g hest priority
mitsubishi electric 16 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 13 interrupt control fig. 14 structure of interrupt polarity selection register brk instruction reset interrupt disable flag i interrupt request bit interrupt enable bit interrupt request not used (returns to 0 when read, do not write 1 in this bit) int 0 interrupt ed g e selection bit int 1 interrupt ed g e selection bit not used (returns to 0 when read, do not write 1 in these bits) 70 interrupt polarity selection re g ister (address 002d 16 ) ipol 0 : fallin g ed g e active 1 : risin g ed g e active for the external interrupts int0 and int1, the active ed g e causin g the interrupt request can be selected by the int0 and int1 interrupt ed g e selection bits of the interrupt polarity selection re g ister (ipol); please refer to fi g . 14 below.
mitsubishi microcomputers 7630 group 17 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 15 structure of interrupt request and control registers a, b and c 7 interrupt request re g ister a (address 0002 16 ) ireqa can wake up interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit 7 0 7 0 0 : no interrupt request 1 : interrupt requested 0 not used (returns to 0 when read) external interrupt int 0 request bit external interrupt int 1 request bit can successful transmission interrupt request bit can successful receive interrupt request bit can overrun interrupt request bit can error passive interrupt request bit can bus off interrupt request bit interrupt request re g ister b (address 0003 16 ) ireqb interrupt request re g ister c (address 0004 16 ) ireqc uart receive complete (receive buffer full) interrupt request bit uart transmit complete (transmit re g ister empty) interrupt request bit uart transmit buffer empty interrupt request bit uart receive error interrupt request bit serial i/o interrupt request bit ad conversion complete interrupt request bit key-on wake-up interrupt request bit not used (returns to 0 when read) 7 0 not used (returns to 0 when read) external interrupt int 0 enable bit external interrupt int 1 enable bit can successful transmission interrupt enable bit can successful receive interrupt enable bit can overrun interrupt enable bit can error passive interrupt enable bit can bus off interrupt enable bit interrupt control re g ister a (address 0005 16 ) icona 7 0 interrupt control re g ister b (address 0006 16 ) iconb can wakeCup interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit 7 0 interrupt control re g ister c (address 0007 16 ) iconc uart receive complete (receive buffer full) interrupt enable bit uart transmit complete (transmit re g ister empty) interrupt enable bit uart transmit buffer empty interrupt enable bit uart receive error interrupt enable bit serial i/o interrupt enable bit ad conversion complete interrupt enable bit key-on wake-up interrupt enable bit not used (returns to 0 when read) 0: interrupt disabled 1: interrupt enabled
mitsubishi electric 18 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer key-on wake-up key-on wake-up is one way of returnin g from a power-down state caused by the stp or wit instruction. any terminal of port p4 can be used to g enerate the key-on wake-up interrupt request. the active polarity can be selected by the key-on wake-up polarity con- trol bit of pcon (see fi g . 12). if any pin of port p4 has the selected active level applied, the key-on wake-up interrupt request will be set to 1. please refer to fi g . 16. fig. 16 block diagram of key-on wake-up circuit pup4 j key-on wake-up interrupt key-on wake-up control bit p4d j port p4 j i/o circuit port p4 j /kw j j = 0 to 7
mitsubishi microcomputers 7630 group 19 mitsubishi electric single-chip 8-bit cmos microcomputer timers the 7630 g roup has five timers: two 16-bit timers and three 8-bit timers . all these timers will be described in detail below. 16-bit timers timers x and y are 16-bit timers with multiple operatin g modes. please refer to fi g . 17. fig. 17 block diagram of timers x and y ( f is internal system clock) timer x timer x is a 16-bit timer with a 16-bit reload latch supportin g the fol- lowin g operatin g modes: (1) timer mode (2) bi-phase counter mode (3) event counter mode (4) pulse width measurement mode these modes can be selected by the timer x mode re g ister (txm). in the timer- and pulse width measurement mode, the timers count source can be selected by the timer x count source selection bits of the timer y mode re g ister (tym). please refer to the fi g ures below for the txm and tym bit assi g nment. on read or write access to timer x, note that the hi g h-order and low- order bytes must be accessed in the specific order. write method when writin g to the timer x, write the low-order byte first. the data written is stored in a temporary re g ister which is assi g ned to the same address as tx l . next, write the hi g h-order byte. when this is finished, the data is placed in the timer x hi g h-order reload latch and the low-order byte is transferred from its temporary re g ister to the timer x low-order reload latch. dependin g on the timer x write control bit, the latch contents are reloaded to the timer immediately (write control bit = 0) or on the next timer underflow (write control bit = 1). read method when readin g the timer x, read the hi g h-order byte first. this causes the timer x hi g h- and low-order bytes to be transferred to temporary re g isters bein g assi g ned to the same addresses as tx h and tx l . next, read the low-order byte which is read from the tem- porary re g ister. this method assures the correct timer value can be read durin g the timer count operation. timer x count stop control re g ardless of the actual operatin g mode, timer x can be stopped by settin g the timer x count stop bit (bit 7 of the timer x mode re g is- ter) to 1. tym 5, 4 =11 tym 7 1/16 1/64 1/128 tym 1,0 f p1 3 /tx 0 p1 4 /cntr 0 edge detector edge detector sign generator tx l counter (8) tx h latch (8) tx h counter (8) txm 7 tx l latch (8) count direction control txm 5, 4 down 00, 10, 11 01 00, 11 01 10 txm 6 txm 5, 4 =11 tx interrupt request cntr0 interrupt request 1/8 1/32 1/64 p1 5 /cntr 1 tym 6 tym 5, 4 10 0x, 11 ty l counter (8) ty h latch (8) ty h counter (8) ty l latch (8) ty interrupt request cntr1 interrupt request rising edge detector falling edge detector tym 5, 4 =01 tym 5, 4 11 0x, 10 0 1 tym 3, 2 1/4 1/2 txm 5,4 00 01 10 11 00 01 10 11 0 1
mitsubishi electric 20 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 18 structure of timer x mode register timer y timer y is a 16 bit timer with a 16-bit reload latch supportin g the fol- lowin g operatin g modes: (1) timer mode (3) event counter mode (5) pulse period measurement mode (6) h/l pulse width measurement mode these modes can be selected by the timer y mode re g ister (tym). in the timer, pulse period- and pulse width measurement modes the timers count source can be selected by the timer y count source selection bits. please refer to fi g . 19. on read or write access to timer y, note that the hi g h-order and low- order bytes must be accessed in a specific order. write method when writin g to timer y, write the low-order byte first. the data writ- ten is stored in a temporary re g ister which is assi g ned to the same address as ty l . next, write the hi g h-order byte. when this is fin- ished, the data is placed in the timer y hi g h-order reload latch and the low-order byte is transferred from its temporary re g ister to the timer y low-order reload latch. read method when readin g the timer y, read the hi g h-order byte first. this causes the timer y hi g h- and low-order bytes to be transferred to temporary re g isters bein g assi g ned to the same addresses as ty h and ty l . next, read the low-order byte which is read from the tem- porary re g ister. this method assures the correct timer value can be read durin g timer count operation. timer y count stop control re g ardless of the actual operatin g mode, timer y can be stopped by settin g the timer y count stop bit (bit 7 of the timer y mode re g is- ter) to 1. timer x data write control bit 0 : data is written to latch and timer 1 : data is written to latch only not used (0 when read, do not write 1) timer x mode bits b5 b4 0 0: timer mode 0 1: bi-phase counter mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 0 polarity selection bit 0 : for event counter mode, risin g ed g e active for interrupt request, fallin g ed g e active for pulse width measurement mode, measure h period 1 : for event counter mode, fallin g ed g e active for interrupt request, risin g ed g e active for pulse width measurement mode, measure l period timer x stop control bit 0 : timer countin g 1 : timer stopped 70 timer x mode re g ister (address 001e 16 ) txm
mitsubishi microcomputers 7630 group 21 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 19 structure of timer y mode register ( f is internal system clock) operatin g modes (1) timer mode this mode is available with timer x and timer y. ? count source the count source for timer x and y is the output of the corre- spondin g clock divider. the division ratio can be selected by the timer y mode re g ister. ? operation both timers x and y are down counters. on a timer underflow, the correspondin g timer interrupt request bit will be set to 1, the contents of the correspondin g timer latches will be reloaded to the counters and countin g continues. (2) bi-phase counter mode (quadruplicate) this mode is available with timer x only. ? count source the count sources are p1 4 /cntr 0 and the p1 3 /tx 0 pins. ? operation timer x will count both risin g and fallin g ed g es on both input pins (see above). refer to timer x bi-phase counter mode operation for the timin g chart of the bi-phase counter mode. the count direction is determined by the ed g e polarity and level of count source inputs and may chan g e durin g the count opera- tion. refer to the table below. on a timer over- or underflow, the correspondin g interrupt request bit will be set to 1 and countin g continues. timer x count source selection bits b1 b0 0 0: f divided by 4 0 1: f divided by 16 1 0: f divided by 64 1 1: f divided by 128 timer y count source selection bits b3 b2 0 0: f divided by 2 0 1: f divided by 8 1 0: f divided by 32 1 1: f divided by 64 timer y operation mode bits b5 b4 0 0: timer mode 0 1: pulse period measurement mode 1 0: event counter mode 1 1: h/l pulse width measurement mode cntr 1 polarity selection bit 0 : for event counter mode, risin g ed g e active for interrupt request, fallin g ed g e active for pulse period measurement mode, refer to fallin g ed g es 1 : for event counter mode, fallin g ed g e active for interrupt request, risin g ed g e active for pulse period measurement mode, refer to risin g ed g es timer y stop control bit 0 : timer countin g 1 : timer stopped 70 timer y mode re g ister (address 001f 16 ) tym table 4: timer x count direction in bi-phase counter mode p1 3 /tx 0 p1 4 /cntr 0 count direction - ed g e lup h down ed g e l down hup l - ed g e down hup l ed g e up h down
mitsubishi electric 22 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 20 timer x bi-phase counter mode operation (3) event counter mode this mode is available with timer x and timer y. ? count source the count source for timer x is the input si g nal to the p1 4 /cntr 0 pin and for timer y the input si g nal to p1 5 /cntr 1 pin. ? operation the timer counts down. on a timer underflow, the correspondin g timer interrupt request bit will be set to 1, the contents of the correspondin g timer latches will be reloaded to the counters and countin g continues. the active ed g e used for countin g can be selected by the polarity selection bit of the correspondin g pin p1 4 /cntr 0 or p1 5 /cntr 1 . these bits are part of txm (structure of timer x mode re g ister) and tym (structure of timer y mode re g ister (f is internal system clock)) re g isters. (4) pulse width measurement mode this mode is available with timer x only. ? count source the count source is the output of timer x clock divider. the divi- sion ratio can be selected by the timer y mode re g ister. ? operation the timer counts down while the input si g nal level on p1 4 /cntr 0 matches the active polarity selected by the cntr 0 polarity selection bit of txm (structure of timer x mode re g is- ter). on a timer underflow, the timer x interrupt request bit will be set to 1, the contents of the timer latches are reloaded to the counters and countin g continues. when the input level chan g es from active polarity (as selected), the cntr 0 interrupt request bit will be set to 1. the measurement result may be obtained by readin g timer x durin g interrupt service. (5) pulse period measurement mode this mode is available with timer y only. ? count source the count source is the output of timer y clock divider. ? operation the active ed g e of input si g nal to be measured can be selected by cntr 1 polarity selection bit (fi g . 18). when this bit is set to 0, the time between two consecutive fallin g ed g es of the si g nal input to p1 5 /cntr 1 pin will be measured, when the polarity bit is set to 1, the time between two consecutive risin g ed g es will be measured. the timer counts down. on detection of an active ed g e of input si g nal, the contents of the ty counters will be transferred to tem- porary re g isters assi g ned to the same addresses as ty. at the same time, the contents of ty latches will be reloaded to the counters and countin g continues. the active ed g e of input si g nal also causes the cntr 1 interrupt request bit to be set to 1. the measurement result may be obtained by readin g timer y durin g interrupt service. (6) h/l pulse width measurement mode this mode is available with timer y only. ? count source the count source is the output of the timer ys clock divider. ? operation this mode measures both the h and l periods of a si g nal input to p1 5 /cntr 1 pin continuously. on detection of any ed g e (risin g or fallin g ) of input si g nal to p1 5 /cntr 1 pin, the contents of timer y counters are stored to temporary re g isters which are assi g ned to the same addresses as timer y. at the same time, the contents of timer y latches are reloaded to the counters and countin g continues. the detection of an ed g e causes the cntr1 interrupt request bit to be set to 1 as well. the result of measurement may be obtained by readin g timer y durin g inter- rupt service. this read access will address the temporary re g is- ters. on a timer underflow, the timer y interrupt request bit will be set to 1, the contents of timer y latches will be transferred to the counters and countin g continues. p1 3 /tx 0 input si g nal p1 4 /cntr 0 input si g nal tx counter count direction down up
mitsubishi microcomputers 7630 group 23 mitsubishi electric single-chip 8-bit cmos microcomputer timer 1, timer 2, timer 3 timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com- mon pre-divider. timer 1 can operate in the timer mode only, whereas timers 2 and 3 can be used to g enerate a pwm output si g - nal timin g as well. timers 1 to 3 are down count timers. see fi g . 21. fig. 21 block diagram of timers 1 to 3 ( f is internal system clock) timer 1 the count source of timer 1 is the output of timer 123 pre-divider. the division ratio of the pre-divider can be selected by the pre- divider division ratio bits of timer 123 mode re g ister (t123m). refer to timer 123 mode re g ister confi g uration (f is internal system clock). on a timer 1 underflow, the timer 1 interrupt request bit will be set to 1. writin g to timer 1 initializes the latch and counter. timers 2 and 3 the count source of timers 2 and 3 can be either the output of the timer 123 pre-divider or the timer 1 underflow. the count source can be selected by the timer count source selection bits of timer 123 mode re g ister (t123m). writin g to timer 2 re g ister affects the reload latch only or both of the reload latch and counter dependin g on the timer 2 write control bit of t123m. when the timer write control bit is set to 0, both latch and counter will be initialized simultaneously; when set to 1 only the reload latch will be initialized, on an underflow, the counter will be set to the modified reload value. writin g to timer 3 initializes latch and counter both. timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to 1. t123m 0 1 1/8 1/32 1/128 t123m 67 f t1 counter (8) t1 latch (8) t2 counter (8) t2 latch (8) t3 counter (8) t3 latch (8) t1 interrupt t2 interrupt t3 interrupt s r q s r q t123m 3 t123m 4 t123m 1 t123m 1 s tq p1 6 /pwm p1 6 latch p1d 6 t123m 1 00 01 10 11 1 0 0 1 1 0 0 1
mitsubishi electric 24 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 22 timer 123 mode register configuration ( f is internal system clock) operating modes (1) timer mode this mode is available with timers 1 to 3. ? count source for timer 1, the count source is the output of the correspondin g pre-divider. for timers 2 and 3, the count source can be sepa- rately selected to be either the pre-divider output or timer 1 underflow. ? operation the timer counts down. on a timer underflow, the correspondin g timer interrupt request bit will be set to 1, the contents of the correspondin g timer latch will be reloaded to the counter and countin g continues. (2) pwm mode this mode is available with timer 2 and 3. ? count source the count source can be separately selected to be either the pre-divider output or timer 1 underflow. ? operation when the pwm-mode is enabled, timer 2 starts countin g . as soon as timer 2 underflows, timer 2 stops and timer 3 starts countin g . if bit 0 is set, timer 2 determines the low duration and the initial output level is low. timer 3 determines the hi g h dura- tion. if bit 0 is zero timer 2 determines the hi g h duration and the initial output level is hi g h. in this case timer 3 determines the low duration. note: be sure to confi g ure the p1 6 /pwm pin as an output port before usin g pwm mode. pwm polarity selection bit 0 : start on h level output 1 : start on l level output pwm output enable bit 0 : pwm output disabled 1 : pwm output enabled timer 2 write control bit 0 : latch and counter 1 : latch only timer 2 count source selection bit 0 : timer 1 underflow 1 : pre-divider output timer 3 count source selection bit 0 : timer 1 underflow 1 : pre-divider output not used (0 when read, do not write 1) pre-divider division ratio bits b7 b6 0 0: f divided by 1 0 1: f divided by 8 1 0: f divided by 32 1 1: f divided by 128 70 timer 123 mode re g ister (address 0019 16 ) t123m
mitsubishi microcomputers 7630 group 25 mitsubishi electric single-chip 8-bit cmos microcomputer serial i/os the serial i/o section of 7630 g roup consists of one clock synchro- nous and one asynchronous (uart) interface. clock synchronous serial i/o (si/o) the clock synchronous interface allows full duplex communication based on 8 bit word len g th. the transfer clock can be selected from an internal or external clock. when an internal clock is selected, a pro g rammable clock divider allows ei g ht different transmission speeds. refer to block dia g ram of clock synchronous i/o (f is inter- nal system clock). the operation of the clock synchronous serial i/o can be confi g ured by the serial i/o control re g ister siocon; refer to fi g . 25. fig. 23 block diagram of clock synchronous i/o ( f is internal system clock) (1) clock synchronous serial i/o operation either an internal or external transfer clock can be selected by bit 6 of siocon. the internal clock divider can be pro g rammed by bits 0 to 2 of siocon. bit 3 of siocon determines whether the double function pins p2 0 to p2 2 will act as i/o ports or serve as sio pins. bit 4 of siocon allows the same selection for pin p2 3 . when an internal transfer clock is selected, transmission can be tri gg ered by writin g data to the si/o shift re g ister (sio, address 0012 16 ). after an 8Cbit transmission has been completed, the s out pin will chan g e to hi g h impedance and the sio interrupt request bit will be set to 1. when an external transfer clock is selected, the sio interrupt request bit will be set to 1 after 8 cycles but the contents of the si/o shift re g ister continue to be shifted while the transfer clock is bein g input. therefore, the clock needs to be controlled externally; the s out pin will not chan g e to hi g h impedance automatically. siocon 2, 1, 0 f sio interrupt sync. circuit p2 3 latch p2 2 /s clk p2 3 /s rdy p2 2 latch sio counter (3) p2 1 /s out p2 1 latch sio shift register (8) p2 0 /s in p2 0 latch siocon 4 siocon 3 siocon 3 siocon 3 siocon 6 clock divider 0 1 0 0 0 0 1 1 1 1
mitsubishi electric 26 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 24 timing of clock synchronous si/o function (lsb first selected) fig. 25 structure of serial i/o control register ( f is internal system clock) clock asynchronous serial i/o (uart) the uart is a full duplex asynchronous transmit/receive unit. the built-in clock divider and baud rate g enerator enable a broad ran g e of transmission speeds. please refer to block dia g ram of uart. (1) description the transmit and receive shift re g isters have a buffer (consistin g of hi g h and low order byte) each. since the shift re g isters cannot be written to or read from directly, transmit data is written to the trans- mit buffer and receive data is read from the receive buffer. a trans- mit or receive operation will be tri gg ered by the transmit enable bit and receive enable bit of the uart control re g ister ucon (see structure of uart control re g ister). the double function terminals p2 5 /ut x d, p2 6 /urts and p2 4 /ur x d, p2 7 /ucts will be switched to serve as uart pins automatically. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 serial input sin serial output sout write signal to sio receive enable signal s rdy transfer clock sio interrupt request bit = 1 note: when an internal clock is selected, s out pin will change to high impedance after 8 bits of data have been transmitted. synchronous clock clock divider selection bits b2 b1 b0 0 0 0: f divided by 4 0 0 1: f divided by 8 0 1 0: f divided by 16 0 1 1: f divided by 32 1 0 0: f divided by 64 1 0 1: f divided by 128 1 1 0: f divided by 256 1 1 1: f divided by 512 p2 0 /s in , p2 1 /s out and p2 2 /s clk function selection bit 0 : i/o port function 1 : si/o function p2 3 /s rdy function selection bit 0 : i/o port function 1 : si/o function transmission order selection bit 0 : lsb first 1 : msb first synchronization clock selection bit 0 : use external clock 1 : use internal clock not used (0 when read) 70 sio control re g ister (address 0013 16 ) siocon
mitsubishi microcomputers 7630 group 27 mitsubishi electric single-chip 8-bit cmos microcomputer (2) baud rate selection the baud rate of transmission and reception is determined by the settin g of the prescaler and the contents of the uart baud rate g enerator re g ister. it is calculated by: where p is the division ratio of the prescaler and n is the content of uart baud rate g enerator re g - ister. the prescalers division ration can be selected by the uart mode re g ister (see below). uart mode register (umod, structure of uart mode register) the uart mode re g ister allows to select the transmission and reception format with the followin g options: ? word len g th: 7, 8 or 9 bits ? parity: none, odd or even ? stop bits: 1 or 2 it allows to select the prescalers division ratio as well. uart baud rate generator (ubrg) this 8 bit re g ister allows to select the baud rate of the uart (see above). set this re g ister to the desired value before enablin g recep- tion or transmission. uart control register (ucon, structure of uart control register) the uart control re g ister consists of four control bits (bit 0 to bit 3) which allow to control reception and transmission. uart status register (usts, structure of uart status register) the read-only uart status re g ister consists of 7 bits (bit 0 to bit 6) which indicate the operatin g status of the uart function and vari- ous errors. (3) handshaking signals when used as transmitter the uart will reco g nize the clear-to- send si g nal via p2 7 /ucts terminal for handshakin g . when used as receiver it will issue a request-to-send si g nal throu g h p2 6 /urts pin. clear-to-send input when used as a transmitter (transmit enable bit set to 1), the uart starts transmission after reco g nizin g l level on p2 7 /ucts . after started the uart will continue to transmit re g ardless of the actual level of p2 7 /ucts or status of the transmit enable bit. request-to-send output the uart controls the p2 6 /urts output accordin g to the followin g conditions. table 5: output control conditions fig. 26 block diagram of uart b f 16 pn 1 + () ---------------------------------- - = condition p2 6 /urts receive enable bit is set to 1 l reception completed durin g receive enable bit set to 1 start bit (fallin g ed g e) detected h receive enable bit is set to 0 before recep- tion started hardware reset receive initialization bit is set to 1 umod 4,3,2 f 1 1/8 1/32 1/256 umod 2, 1 ubrg (8) transmit shift register (9) transmission control circuit reception control circuit p2 5 /utxd p2 7 /ucts p2 6 /urts bit counter bit counter umod 7, 6 umod 7, 6 uart status register transmit buffer empty flag receive error flags receive buffer full interrupt request receive error interrupt request p2 4 /urxd transmit buffer (9) data bus data bus transmit buffer empty interrupt request transmit register empty interrupt request receive buffer full flag transmit register empty flag receive shift register (9) receive buffer (9) uart control register 00 01 10 11
mitsubishi electric 28 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 27 structure of uart mode register fig. 28 structure of uart control register not used (0 when read, do not write 1) clock divider selection bits b2 b1 0 0 : f divided by 1 0 1 : f divided by 8 1 0 : f divided by 32 1 1 : f divided by 256 stop bits selection bit 0 : one stop bit 1 : two stop bits parity selection bit 0 : even parity 1 : odd parity parity enable bit 0 : parity disabled 1 : parity enabled uart word len g th selection bits b7 b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : not used 70 uart mode re g ister umod (address 0020 16 ) transmit enable bit 0 : transmit disabled (an on g oin g transmission will be finished correctly) 1 : transmit enabled receive enable bit 0 : receive disabled (an on g oin g reception will be finished correctly) 1 : receive enabled transmission initialization bit 0 : no action 1 : clear transmit buffer full fla g and transmit shifter full fla g , set the transmit status re g ister bits and stop transmission receive initialization bit 0 : no action 1 : clear receive status fla g s and the receive enable bit not used (0 when read, do not write 1) 70 uart control re g ister ucon (address 0022 16 )
mitsubishi microcomputers 7630 group 29 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 29 structure of uart status register transmit re g ister empty fla g 0 : re g ister full 1 : re g ister empty transmit buffer empty fla g 0 : buffer full 1 : buffer empty receive buffer full fla g 0 : buffer full 1 : buffer empty receive parity error fla g 0 : no parity error detected 1 : parity error detected receive framin g error fla g 0 : no framin g error detected 1 : framin g error detected receive overrun fla g 0 : no overrun detected 1 : overrun detected receive error sum fla g 0 : no error detected 1 : error detected not used (0 when read) note: this re g ister is read only; writin g does not affect its contents. 70 uart status re g ister (address 0023 16 ) usts
mitsubishi electric 30 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer can module the can (controller area network) interface of the 7630 g roup complies with the 2.0b specification, enablin g reception and trans- mission of frames with either 11- or 29- bit identifier len g th. refer to fi g . 31 for a block dia g ram of the can interface. the pro g rammers interface to the can module is formed by three status/control re g isters (fi g . 32, fi g . 33, fi g . 34), two bus timin g control re g isters (fi g . 35 fi g . 36), several re g isters for acceptance filterin g (fi g . 37), the transmit and receive buffer re g isters (fi g . 38) and one dominant level control bit (fi g . 22). baud rate selection a pro g rammable clock prescaler is used to derive the can mod- ules basic clock from the internal system clock frequency ( f ). bit 0 to bit 3 of the can bus timin g control re g ister represent the pres- caler allowin g a division ratio from 1 to 1/16 to be selected. so the can module basic clock frequency f canb can be calculated as fol- lows: where p is the value of the prescaler (selectable from 1 to 15). the effective baud rate of the can bus communication depends on the can bus timin g control parameters and will be explained below. can bus timing control each bit-time consists of four different se g ments (see fi g . 30): ? synchronization se g ment (ss), ? propa g ation time se g ment (pts), ? phase buffer se g ment 1 (pbs1) and ? phase buffer se g ment 2 (pbs2). fig. 30 bit time of can module the first of these se g ments is of fixed len g th (one time quantum) and the latter three can be pro g rammed to be 1 to 8 time quanta by the can bus timin g control re g ister 1 and 2 (see fi g . 35 and fi g . 36). the whole bit-time has to consist of minimum 8 and maximum 25 time quanta. the duration of one time quantum is the cycle time of f canb . for example, assumin g f = 5 mhz, p = 0, one time quantum will be 200 ns lon g . this allows the maximum transmis- sion rate of 625 kb/s to be reached (assumin g 8 time quanta per bit-time). fig. 31 block diagram of can module f canb f p 1 + ----------- - = ss pts pbs1 pbs2 sample point bit-time bus timing control register data bus acceptance mask register acceptance code register transmit buffer receive buffer 1 receive buffer 2 acceptance filter data bus p3 1 /ctx p3 2 /crx protocol controller can wake-up wake-up logic polarity control register can status/control registers
mitsubishi microcomputers 7630 group 31 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 32 structure of can transmit control register 70 can transmit control re g ister (address 0030 16 ) ctrm sleep control bit 0 : can module in normal mode 1 : can module in sleep mode reset/confi g uration control bit 0 : can module in normal mode 1 : can module in confi g uration mode (plus reset at write) port double function control bit 0 : p3 1 /ctx serves as i/o port 1 : p3 1 /ctx serves as ctx output port transmit request bit 0 : no transmission requested 1 : transmission requested (write 0 has no effect) not used (no operation, 0 when read) transmit buffer control bit 0 : cpu access possible 1 : no cpu access (write 0 has no effect, while ctrm(3) = 1) not used (no operation, 0 when read) transmit status bit (read only) 0 : can module idle or receivin g 1 : can module transmittin g
mitsubishi electric 32 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 33 structure of can receive control register fig. 34 structure of can transmit abort register 70 can receive control re g ister (address 003d 16 ) crec receive buffer control bit 0 : receive buffer empty 1 : receive buffer full (write 1 has no effect) receive status bit (read only) 0 : can module idle or transmittin g 1 : can module receivin g not used (do not write 1, read as 0) auto-receive disable bit 0 : auto-receive enabled 1 : auto-receive disabled note: suppresses reception of self initiated/transmitted frames not used (do not write 1, 0 when read) 70 can transmit abort re g ister (address 003e 16 ) cabort transmit abort control bit 0 : no transmit abort request 1 : transmit abort request (write 1 has no effect, while ctrm(3) = 0) not used (no operation, 0 when read)
mitsubishi microcomputers 7630 group 33 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 35 structure of can bus timing control register 1 fig. 36 structure of can bus timing control register 2 70 can bus timin g control re g ister 1 (address 0031 16 ) cbtcon1 prescaler division ratio selection bits b3 b2 b1 b0 0 0 0 0: f divided by 1 0 0 0 1: f divided by 2 0 0 1 0: f divided by 3 1 1 1 0: f divided by 15 1 1 1 1: f divided by 16 samplin g control bit 0 : one sample per bit 1 : three sample per bit propa g ation time duration control bits b7 b6 b5 0 0 0: one time quantum 0 0 1: two time quanta 1 1 0: seven time quanta 111: ei g ht time quanta 70 can bus timin g control re g ister 2 (address 0032 16 ) cbtcon2 phase buffer se g ment 1 duration control bits b2 b1 b0 0 0 0: one time quantum 0 0 1: two time quanta 1 1 0: seven time quanta 111: ei g ht time quanta phase buffer se g ment 2 duration control bits b5 b4 b3 0 0 0: one time quantum 0 0 1: two time quanta 1 1 0: seven time quanta 111: ei g ht time quanta synchronization jump width control bits b7 b6 0 0 : one time quantum 0 1 : two time quanta 1 0 : three time quanta 1 1 : four time quanta
mitsubishi electric 34 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 37 structure of can mask and code registers fig. 38 structure of can transmission and reception buffer registers address 7 0 not used not used not used csid 10 csid 9 csid 8 csid 7 csid 6 csid 5 csid 4 csid 3 csid 2 csid 1 csid 0 not used not used not used not used not used not used ceid 17 ceid 16 ceid 15 ceid 14 ceid 13 ceid 12 ceid 11 ceid 10 ceid 9 ceid 8 ceid 7 ceid 6 ceid 5 ceid 4 ceid 3 ceid 2 ceid 1 ceid 0 not used not used 7 0 not used not used not used msid 10 msid 9 msid 8 msid 7 msid 6 msid 5 msid 4 msid 3 msid 2 msid 1 msid 0 not used not used not used not used not used not used meid 17 meid 16 meid 15 meid 14 meid 13 meid 12 meid 11 meid 10 meid 9 meid 8 meid 7 meid 6 meid 5 meid 4 meid 3 meid 2 meid 1 meid 0 not used not used 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 acceptance code registers: acceptance mask registers: select the bit pattern of identifiers which allows to pass acceptance filterin g . 0 : mask identifier bit (do not care) 1 : compare identifier bit with acceptance code re g ister bit (not used: write to 0) name cac0 cac1 cac2 cac3 cac4 cam0 cam1 cam2 cam3 cam4 offset 7 0 not used not used not used sid 10 sid 9 sid 8 sid 7 sid 6 sid 5 sid 4 sid 3 sid 2 sid 1 sid 0 rtr/srr ide not used not used not used not used eid 17 eid 16 eid 15 eid 14 eid 13 eid 12 eid 11 eid 10 eid 9 eid 8 eid 7 eid 6 eid 5 eid 4 eid 3 eid 2 eid 1 eid 0 rtr r1 0000 16 0001 16 0002 16 0003 16 0004 16 not used not used not used r 0 dlc 3 dlc 2 dlc 1 dlc 0 0005 16 0006 16 data byte 0 0007 16 data byte 1 0008 16 data byte 2 0009 16 data byte 3 000a 16 data byte 4 000b 16 data byte 5 000c 16 data byte 6 000d 16 data byte 7 calculate the actual address as follows: txd buffer address = 0040 16 + offset rxd buffer address = 0050 16 +offset (not used: write to 0) name ctb0, crb0 ctb1, crb1 ctb2, crb2 ctb3, crb3 ctb4, crb4 ctb5, crb5 ctb6, crb6 ctb7, crb7 ctb8, crb8 ctb9, crb9 ctba, crba ctbb, crbb ctbc, crbc ctbd, crbd note 1: all can related sfrs must not be written in can sleep mode.
mitsubishi microcomputers 7630 group 35 mitsubishi electric single-chip 8-bit cmos microcomputer a-d converter the a-d converter uses the successive approximation method with 8 bit resolution. the functional blocks of the a-d converter are described below. refer to block dia g ram of a-d converter. comparison voltage generator the comparison volta g e g enerator divides the volta g e between av ss and v ref by 256, and outputs the divided volta g e. channel selector the channel selector selects one of ports p0 0 /an 0 to p0 7 /an 7 , and inputs its volta g e to the comparator. a-d conversion register ad the a-d conversion re g ister is a read-only re g ister that stores the result of an a-d conversion. this re g ister must not be read durin g an a-d conversion. fig. 39 block diagram of a-d converter a-d control register (structure of a-d control reg- ister) the a-d control re g ister controls the a-d conversion process. bits 0 to 2 select a specific analo g input pin. bit 3 si g nals the completion of an a-d conversion. the value of this bit remains 0 durin g an a- d conversion, and chan g es to 1 when an a-d conversion ends. writin g 0 to this bit starts the a-d conversion. bit 4 is the v ref / input switch bit. av ss p0 0 /an 0 3 a-d control register b7 b0 comparison voltage generator a-d control circuit comparator p0 7 /an 7 v ref a-d interrupt request a-d conversion register channel selector data bus v ref /input switch bit
mitsubishi electric 36 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 40 structure of a-d control register a-d converter operation the comparator and control circuit reference an analo g input volt- a g e with the reference volta g e, then stores the result in the a-d conversion re g ister. when an a-d conversion is complete, the con- trol circuit sets the a-d conversion completion bit and the a-d inter- rupt request bit to 1. the result of a-d conversion can be obtained from the a-d conversion re g ister, ad (address 0014 16 ). note that the comparator is linked to a capacitor, so set f(x in ) to 500 khz or hi g her durin g a-d conversion. 70 a-d control re g ister (address 0015 16 ) adcon analo g input pin selection bits b2 b1 b0 0 0 0 : p0 0 /an 0 0 0 1 : p0 1 /an 1 0 1 0 : p0 2 /an 2 0 1 1 : p0 3 /an 3 1 0 0 : p0 4 /an 4 1 0 1 : p0 5 /an 5 1 1 0 : p0 6 /an 6 1 1 1 : p0 7 /an 7 a-d conversion completion bit 0 : conversion in pro g ress 1 : conversion completed v ref /input switch bit 0 : off 1 : on not used (0 when read, do not write 1)
mitsubishi microcomputers 7630 group 37 mitsubishi electric single-chip 8-bit cmos microcomputer watchdog timer the watchdo g timer consists of two separate counters: one 7-bit counter (wd h ) and one 4-bit counter (wd l ). cascadin g both counters or usin g the hi g h-order counter allows only to select the time-out from either 524288 or 32768 cycles of the internal clock f . refer to fi g . 41 and fi g . 42. both counters are addressed by the same watchdo g timer re g ister (wdt). when writin g to this re g ister, both counters will be set to the followin g default values: ?the hi g h-order counter will be set to address 7f 16 ? the low-order counter will be set to address f 16 re g ardless of the data written to the wdt re g ister. readin g the watchdo g timer re g ister will return the correspondin g control bit sta- tus, not the counter contents. once the wdt re g ister is written to, the watchdo g timer starts countin g down and the watchdo g timer interrupt is enabled. once it is runnin g , the watchdo g timer cannot be disabled or stopped except by reset. on a watchdo g timer underflow, a non-maskable watchdo g timer interrupt will be requested. to prevent the system bein g stopped by stp instruction, this instruction can be disabled by the stp instruction disable bit of wdt re g ister. once the stp instruction is disabled, it cannot be enabled a g ain except by reset. fig. 41 block diagram of watchdog timer fig. 42 structure of watchdog timer register ( f is internal clock system) 1/256 f wdt interrupt wd l counter (4) wd h counter (7) wdt 7 f 16 7f 16 wdt register (8) 0 1 not used (undefined when read) stop instruction disable bit 0 : stop instruction enabled 1 : execute two nop instructions instead (once this bit is set to 1 it can not be cleared to 0 a g ain, except on reset.) upper byte count source selection bit 0 : underflow of the low order counter 1 : f divided by 256 70 watchdo g timer re g ister (address 002e 16 ) wdt
mitsubishi electric 38 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer reset circuit the 7630 g roup is reset accordin g to the sequence shown in fi g . 44. it starts pro g ram execution from the address formed by the con- tents of the addresses fffb 16 and fffa 16 , when the reset pin is held at l level for more than 2 m s while the power supply volta g e is in the recommended operatin g condition and then returned to h level. refer to fi g . 43 for an example of the reset circuit. fig. 43 example of reset circuit fig. 44 reset sequence power on 0v 0v power source voltage reset input voltage 4.0v 0.8v 7630 group m51953al reset v ss v cc 0.1 m f 1 5 4 3 x in reset internal reset address data ????? ????? 28 to 34 cycles of x in ad l ad h fffa 16 fffb 16 ad l , ad h 1st op code 20 cycles of x in 24 cycles of x in 8192 cycles of x in (t1, t2)
mitsubishi microcomputers 7630 group 39 mitsubishi electric single-chip 8-bit cmos microcomputer fig. 45 internal status of microcomputer after reset register address register contents timer xh 001b 16 ff 16 timer yl 001c 16 ff 16 timer yh 001d 16 ff 16 timer x mode reg. 001e 16 00 16 timer y mode reg. 001f 16 00 16 uart mode reg. 0020 16 00 10 uart control reg. 0022 16 00 16 uart status reg. 0023 16 07 10 port p0 pull-up control reg. 0028 16 00 16 port p1 pull-up control reg. 0029 16 00 16 port p2 pull-up control reg. 002a 16 00 16 port p3 pull-up control reg. 002b 16 00 16 port p4 pull-up/down control reg. 002c 16 00 16 interrupt polarity selection reg. 002d 16 00 16 watchdog timer reg. 002e 16 3f 16 polarity control reg. 002f 16 00 16 can transmit control reg. 0030 16 02 16 can bus timing control reg. 1 0031 16 00 16 can bus timing control reg. 2 0032 16 00 16 can receive control reg. 003d 16 00 16 can transmit abort reg. 003e 16 00 16 processor status reg. (ps) 04 16 program counter (high-order byte) (pch) contents of fffb 16 program counter (low-order byte) (pcl) contents of fffa 16 register address register contents cpu mode reg. 0000 16 48 16 interrupt request reg. a 0002 16 00 16 interrupt request reg. b 0003 16 00 16 interrupt request reg. c 0004 16 00 16 interrupt control reg. a 0005 16 00 16 interrupt control reg. b 0006 16 00 16 interrupt control reg. c 0007 16 00 16 port p0 reg. 0008 16 00 16 port p0 direction reg. 0009 16 00 16 port p1 reg. 000a 16 00 16 port p1 direction reg. 000b 16 00 16 port p2 reg. 000c 16 00 16 port p2 direction reg. 000d 16 00 16 port p3 reg. 000e 16 00 16 port p3 direction reg. 000f 16 00 16 port p4 reg. 0010 16 00 16 port p4 direction reg. 0011 16 00 16 serial i/o control reg. 0013 16 00 16 a-d control reg. 0015 16 08 16 timer 1 0016 16 ff 16 timer 2 0017 16 01 16 timer 3 0018 16 ff 16 timer 123 mode reg. 0019 16 40 16 timer xl 001a 16 ff 16 note: the contents of ram and re g isters other than the above re g isters are undefined after reset; thus software initialization is required.
mitsubishi electric 40 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer clock generating circuit the 7630 g roup is equipped with an internal clock g eneratin g cir- cuit. please refer to fi g . 46 for a circuit example usin g a ceramic resona- tor or quartz crystal oscillator. for the capacitor values, refer to the manufacturers recommended parameters which depend on each oscillators characteristics. when usin g an external clock, input it to the x in pin and leave x out open. fig. 46 ceramic resonator circuit . oscillation control the 7630 g roup has two low power modes: the stop and the wait mode. stop mode the microcomputer enters the stop mode by executin g the stp instruction. the oscillator stops with the internal clock f at h level. timers 1 and 2 will be cascaded and initialized by their reload latches contents. the count source for timer 1 will be set to f(x in )/16. oscillation is restarted if an external interrupt is accepted or at reset. when usin g an external interrupt, the internal clock f remains at h level until timer 2 underflows allowin g a time-out until the clock oscillation becomes stable. when usin g reset, a fixed time-out will be g enerated allowin g oscillation to stabilize. wait mode the microcomputer enters the wait mode by executin g the wit instruction. the internal clock ? stops at h level while the oscillator keeps runnin g . recovery from wait mode can be done in the same way as from stop mode. however, the time-out period mentioned above is not required to return from wait-mode, thus no such time-out mecha- nism has been implemented. note: set the interrupt enable bit of the interrupt source to be used to return from stop or wait mode to 1 before executin g stp or wit instruction. fig. 47 block diagram of clock generating circuit c in c out x in x out wit stp x in x out 1/2 1/4 cpum 6 interrupt request interrupt disable flag s r q reset delay stp d t q d t q r s q r s q r s q stp p2 internal clock for peripherals internal clock for cpu oscillator countdown (timer 1 and 2) 2 f f 1 0
mitsubishi microcomputers 7630 group 41 mitsubishi electric single-chip 8-bit cmos microcomputer data required for mask orders the followin g are necessary when orderin g a mask rom produc- tion: 1 mask rom order confirmation form 2 mark specification form 3 contents of mask rom, in eprom form (three identical copies) prom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or pro g rammed with a g eneral pur- pose prom pro g rammer usin g a special pro g rammin g adapter. set the address of prom pro g rammer to the user rom area. for the pro g rammin g adapter type name, please refer to the follow- in g table: the prom of the blank one time prom version is not tested or screened in the assembly process and followin g processes. to ensure proper operation after pro g rammin g , the procedure shown in fi g . 48 is recommended to verify pro g rammin g . fig. 48 programming and testing of one time prom version table 6: programming adapter name mcu type packa g epro g rammin g adapter type one time prom 44p6n-a pca7430 eprom 80d0 pca7431 programming with prom programmer screening *(note) (150 c for 40 hours) verification with prom programmer functional test in target unit note on screening: the screening temperature is far higher than the storage temper- ature. never subject the device to 150 c exceeding 100 hours.
mitsubishi electric 42 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer table 7: absolute maximum ratings table 8: recommended operating conditions symbol parameter conditions ratin g sunit v cc power source volta g e all volta g es with respect to v ss and output transistors are off. C0.3 to 7.0 v v i input volta g ep0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset , x in C0.3 to v cc + 0.3 v v o output volta g ep0 0 p0 7 , p1 2 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , x out C0.3 to v cc + 0.3 v p d power dissipation ta = 25 c 500 mw t opr operatin g temperature C40 to 85 c t stg stora g e temperature C60 to 150 c symbol parameter limits unit min. typ. max. v cc power source volta g e 4.0 5.0 5.5 v v ss 0v v ih h input volta g e p0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset , x in 0.8 v cc v cc v v il l input volta g e p0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset , x in 0 0.2 v cc v ? i oh (peak) h sum peak output current p0 0 p0 7 , p1 2 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 C80 ma ? i oh (av g ) h sum avera g e output current C40 ma ? i ol (peak) l sum peak output current 80 ma ? i ol (av g ) l sum avera g e output current 40 ma i oh (peak) h peak output current C10 ma i oh (av g ) h avera g e output current C5 ma i ol (peak) l peak output current 10 ma i ol (av g ) l avera g e output current 5ma i io input current at overvolta g e condi- tion (v i > v cc ) p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 1ma ? i io total input current at overvolta g e condition (v i > v cc ) p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 16 ma f(cntr) timer input frequency (based on 50 % duty) p1 4 /cntr 0 , p1 5 /cntr 1 (except bi-phase counter mode) f(x in )/16 mhz p1 3 /tx 0 , p1 4 /cntr 0 (bi-phase counter mode) f(x in )/32 mhz f(x in ) clock input oscillation frequency 10 mhz (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, t a = C 40 to 85 c unless otherwise noted)
mitsubishi microcomputers 7630 group 43 mitsubishi electric single-chip 8-bit cmos microcomputer table 9: electrical characteristics symbol parameter test conditions limits unit min. typ. max. v oh h output volta g e p0 0 p0 7 , p1 2 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 i oh = C5 ma 0.8 v cc v v ol l output volta g e p0 0 p0 7 , p1 2 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 i ol = 5 ma 2.0 v v t+ C v tC hysteresis p1 1 /int 0 , p1 2 /int 1 , p1 3 /tx 0 , p1 4 /cntr 0 , p1 5 /cntr 1 ,p2 0 /s in , p2 2 /s clk , p2 6 /u rts , p2 7 /u cts , p3 2 /crx, reset 0.5 v i ih h input current p0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset v i = v cc 5 m a i ih h input current x in v i = v cc 4 m a i il l input current p0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset v i = v ss C5 m a i il l input current x in v i = v ss C4 m a i ih h input current p3 2 , p4 0 p4 7 v i = v cc pull-down = on 20 200 m a i il l input current p0 0 p0 7 , p1 1 p1 7 , p2 0 p2 7 , p3 0 p3 4 , p4 0 p4 7 , reset v i = v ss pull-up = on -200 -20 m a v ram ram hold volta g e when clock stopped 2.0 v (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, t a = C 40 to 85 c unless otherwise noted)
mitsubishi electric 44 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer i cc power source current high speed mode, f(x in )=8mhz, v cc =5v, output transistors off, can module running, adc running 11.0 18.0 ma high speed mode, f(x in )=8mhz, v cc =5v, output transistors off, can module stopped, adc running 9.0 16.0 ma middle speed mode, f(x in )=8mhz, v cc =5v, output transistors off, can module running, adc running 6.0 11.0 ma middle speed mode, wait mode, f(x in )=8mhz, v cc = 5v, output transis- tors off, can module stopped, adc stopped 2.0 ma stop mode, f(x in )=0mhz, v cc =5v, t a =25 c 0.1 1.0 m a stop mode, f(x in )=0mhz, v cc =5v, t a =85 c 10.0 m a symbol parameter test conditions limits unit min. typ. max. table 10: a-d converter characteristics symbol parameter test conditions limits unit min. typ. max. resolution 8bit absolute accuracy 1.0 2.5 lsb t conv conversion time highCspeed mode 106 108 t c (x in ) middleCspeed mode 424 432 t c (x in ) v ref reference input volta g e2.0 v cc v i ref reference input current v cc = v ref = 5.12 v 150 200 m a r ladder ladder resistor value 35 k w i ian analo g input current v i = v ss to v cc 0.5 5.0 m a (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, t a = C40 to 85 c, unless otherwise noted)
mitsubishi microcomputers 7630 group 45 mitsubishi electric single-chip 8-bit cmos microcomputer table 11: timing requirements symbol parameter limits unit min. typ. max. t w (reset ) reset input l pulse width 2 m s t c (x in ) external clock input cycle time 100 ns t wh (x in ) external clock input h pulse width 37 ns t wl (x in ) external clock input l pulse width 37 ns t c (cntr) cntr 0 , cntr 1 input cycle time (except bi-phase counter mode) 1600 ns cntr 0 input cycle time (bi-phase counter mode) 2000 ns t wh (cntr) cntr 0 , cntr 1 input h pulse width (except bi-phase counter mode) 800 ns cntr 0 input h pulse width (bi-phase counter mode) 1000 ns t wl (cntr) cntr 0 , cntr 1 input l pulse width (except bi-phase counter mode) 800 ns cntr 0 input l pulse width (bi-phase counter mode) 1000 ns t l (cntr 0 -tx 0 ) la g of cntr 0 and tx 0 input ed g es (bi-phase counter mode) 500 ns t c (tx 0 )tx 0 input cycle time (bi-phase counter mode) 3200 ns t wh (tx 0 )tx 0 input h pulse width (bi-phase counter mode) 1600 ns t wl (tx 0 )tx 0 input l pulse width (bi-phase counter mode) 1600 ns t wh (int) int 0 , int 1 input h pulse width 460 ns t wl (int) int 0 , int 1 input l pulse width 460 ns t c (s clk ) serial i/o clock input cycle time 8t c (x in ) ns t wh (s clk ) serial i/o clock input h pulse width 4t c (x in ) ns t wl (s clk ) serial i/o clock input l pulse width 4t c (x in ) ns t su (s in Cs clk ) serial i/o input setup time 200 ns t h (s clk Cs in ) serial i/o input hold time 150 ns (v cc =4.0 to 5.5 v, v ss =av ss =0 v, t a =C40 to 85 c unless otherwise noted)
mitsubishi electric 46 mitsubishi microcomputers 7630 group single-chip 8-bit cmos microcomputer fig. 49 circuit for measuring output switching characteristics table 12: switching characteristics symbol parameter limits unit min. typ. max. t wh (s clk ) serial i/o clock output h pulse width 0.5 t c (s clk )C50 ns t wl (s clk ) serial i/o clock output l pulse width 0.5 t c (s clk )C50 ns t d (s clk Cs out ) serial i/o output delay time 50 ns t v (s clk Cs out ) serial i/o output valid time 0 50 ns t r (s clk ) serial i/o clock output rise time 50 ns t r (cmos) cmos output rise time 10 50 ns t f (cmos) cmos output fall time 10 50 ns measurement output pin 100 pf cmos output (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, t a = C40 to 85 c, unless otherwise noted)
mitsubishi microcomputers 7630 group 47 mitsubishi electric single-chip 8-bit cmos microcomputer timing diagram fig. 50 timing diagram t wl (int) t wh (int) 0.8v cc 0.2v cc t wl (reset ) 0.2v cc t wl (x in ) t wh (x in ) 0.8v cc 0.2v cc t c (x in ) 0.8v cc 0.2v cc t wl (s clk )t wh (s clk ) t c (s clk ) t f t r 0.2v cc 0.8v cc t su (s in -s clk ) t h (s clk -s in ) t d (s clk -s out )t v (s clk -s out ) s out s in s clk x in reset int 0 , int 1 t wl (cntr) t wh (cntr) 0.8v cc 0.2v cc cntr 0 , cntr 1 t c (cntr) t wl (tx 0 ) t wh (tx 0 ) 0.8v cc 0.2v cc tx 0 t c (tx 0 )
1 revision report m37630 e4/m4 revision 7630 english data sheets revision date page modifications 1.1 10. 98 can controller is replaced by can module in whole document. 11 11 schematics (8) and (11) are corrected. 18 18 replaced: pupd j with pup4 j 26 26 replaced: ut x d with sout replaced: ur x d with sin 38 38 replaced: fffb h with fffb 16 replaced: fffa h with fffa 16 41 replaced: 44p6n with 44p6n-a) (1.2) 13.01.99 43 43 values changed:iih(35, 113) to (20, 200) and iil(-122, -70) to (-200, -20); typical values are removed. 10 10 schematic (1) is modified. 35 35 fig. 39 is modified. new old

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